The MOD 10 Counter
The technique for designing a MOD 10 counter is introduced. Asynchronous inputs of a JK flip-flop are used to clear the counter.
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How would I Design a FSM Controller to drive the two signals ld_en and CLR . The
Controller should have a single input clr/shift and operate as follows: When clr/shift = 1 both Shift Registers are loaded via their Parallel Inputs.
When clr/shift = 0 each rising clock shifts the value in both SR.